The present invention relates to a clock circuit, and in particular to a clock circuit using a phase-locked loop (PLL).
Conventionally, for a logic circuit such as a semiconductor integrated circuit, of a large scale and operating at a high speed, including a circuit of a large lead capacitance, and requiring supply of high-frequency clocks, it has been proposed to use a clock circuit using a PLL circuit to reduce the skew between the basic clock such as an external clock and the local clocks in the logic circuit, and the clock skew between the local clocks within the logic circuit.
A clock circuit including such a PLL circuit is described in for example an article "Use of a PLL in a 0.5 .mu.m ASIC: Interface Design as a Crux of Speed Increase" in Nikkei Micro Devices. February 1993, pp. 81-85. However, the above-described clock circuit is associated with the following problems.
(a) When the clock circuit is active, a large lead capacitance is directly connected to the local clock output terminal. Accordingly, there is a substantial power consumption. PA0 (b) If, in a stand-by state of the clock circuit, the operation of time clock circuit including the PLL circuit is inhibited to reduce the power consumption, a waiting time for the pull-in time of the PLL circuit for resuming the active state from the stand-by state will be required. This pull-in time is very long compared with the period of the clock (e.g., several hundreds of micro-seconds for the clock of 100 MHz), and a high-speed operation of the system including the clock circuit is prevented. If, the clock circuit including the PLL circuit is kept operating even in the stand-by state, in order to shorten the time required for transition from the stand-by state to the active state, substantial power as in the active state is consumed in the stand-by state.